A design algorithm for sequential circuits using LUT rings

被引：0

作者：

Nakahara, H ^{[1
]}

Sasao, T ^{[1
]}

Matsuura, M ^{[1
]}

机构：

[1] Kyushu Inst Technol, Dept Comp Sci & Engn, Iizuka, Fukuoka 8208502, Japan

来源：

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | 2005年 / E88A卷 / 12期

关键词：

reconfigurable architecture; LUT cascade; BDD_for_CF; functional decomposition;

D O I：

10.1093/ietfec/e88-a.12.3342

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper shows a design method for a sequential circuit by using a Look-Up Table (LUT) ring. The method consists of two steps: The first step partitions the outputs into groups. The second step realizes them by LUT cascades, and allocates the cells of the cascades into the memory. The system automatically finds a fast implementation by maximally utilizing available memory. With the presented algorithm, we can easily design sequential circuits satisfying given specifications. The paper also compares the LUT ring with logic simulator to realize sequential circuits: the LUT ring is 25 to 237 times faster thin a logic simulator that uses the same amount of memory.

引用

页码：3342 / 3350

页数：9

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