In this paper, the modeling approaches for first-level solder interconnects in shock and drop of electronics assemblies have been developed without any assumptions of geometric-symmetry or loading symmetry. The problem involves multiple scales from macro-scale transient-dynamics of electronic assembly to micro-structural damage history of interconnects. Previous modeling approaches include, solid-to-solid sub-modeling [Zhu, et. at. 2001] using a half test PCB board, shell-to-solid sub-modeling technique using a quarter-symmetry model [Ren, et. al. 2003, 2004]. Inclusion of model symmetry in state-of-art models saves computational time, but targets primarily symmetric mode shapes. The modeling approach proposed in this paper enables prediction of both symmetric and anti-symmetric modes, which may dominate an actual drop-event. Approaches investigated include, smeared property models, Timoshenko-beam element models, explicit sub-models, and continuum-shell models. Transient dynamic behavior of the board assemblies in free and JEDEC-drop has been measured using high-speed strain and displacement measurements. Model predictions have been correlated with experimental data.