Cellular handset integration - SIP vs. SOC and best design practices for SIP

被引:0
|
作者
Lyne, K [1 ]
机构
[1] Texas Instruments Inc, Dallas, TX 75243 USA
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
There has recently been much discussion regarding the pros and cons of Silicon on Chip (SOC) verses System in Package (SIP). SOC is firstly driven by cost reduction and secondly by miniaturization. This involves cost reduction at component level as well at system (handset) level. Cost reduction comes from a reduction of total component count, both ICs and passives, as well as reduction in mother board area. Further cost avoidance comes from a bill of materials with few components, giving the benefits of lower surface mounting costs, and lower inventory overhead. Similarly, SIP can offer some of these benefits. However, in most cases, the primary motivation for SIP is miniaturization, rather than cost reduction. An aggressive goal for a SIP product would be to achieve the same cost for the SIP as the sum of the elements integrated in to the SIP. Even if this aggressive cost goal is not achieved, the benefits from the miniaturization are frequently sufficient to justify the development of a SIP product. In reality, there is no conflict between the SOC and SIP technologies. Many times both techniques are employed synergistically. This paper continues this SOC vs SIP discussion, focusing on SIP, and demonstrating the synergism between the two.
引用
下载
收藏
页码:765 / 770
页数:6
相关论文
共 45 条
  • [11] Mobility management for VoIP service: Mobile IP vs. SIP
    Kwon, TT
    Gerla, M
    Das, S
    Das, S
    IEEE WIRELESS COMMUNICATIONS, 2002, 9 (05) : 66 - 75
  • [12] Heterogeneous Chiplet Design and Integration Bringing a New Twist to SiP Design
    Felton, Keith
    Mastroianni, Anthony
    Rinebold, Kevin
    Viklund, Per
    Advancing Microelectronics, 2022, 49 (02): : 10 - 14
  • [13] Standard bus vs. bus wrapper: What is the best solution for future SoC integration?
    Yeung, C
    Matthews, G
    Morris, J
    Haverinen, A
    Zaidi, J
    DESIGN, AUTOMATION AND TEST IN EUROPE, CONFERENCE AND EXHIBITION 2001, PROCEEDINGS, 2001, : 776 - 776
  • [14] System I/O Optimization with SoC, SiP, PCB Co-Design
    Mandavia, Humair
    Koga, Kazunari
    Bruening, Ralf
    Kontic, Nikola
    2015 EUROPEAN MICROELECTRONICS PACKAGING CONFERENCE (EMPC), 2015,
  • [15] System I/O optimization with SoC, SiP, PCB co-design
    Wang, Lance
    Advancing Microelectronics, 2019, 46 (06): : 16 - 20
  • [16] BEST PRACTICES David vs. Goliath
    Pofeldt, Elaine
    FORTUNE, 2011, 163 (06) : 22 - 22
  • [17] BEST PRACTICES David vs. Goliath
    Shambora, Jessica
    FORTUNE, 2010, 161 (04) : 68 - 68
  • [18] BEST PRACTICES David vs. Goliath
    Shambora, Jessica
    FORTUNE, 2010, 162 (09) : 69 - 69
  • [19] BEST PRACTICES David vs. Goliath
    Shambora, Jessica
    FORTUNE, 2010, 162 (06) : 69 - 69
  • [20] BEST PRACTICES DAVID VS. GOLIATH
    Pofeldt, Elaine
    FORTUNE, 2011, 164 (07) : 50 - 50