A single-chip universal digital satellite receiver with 480-MHz IF input

被引：5

作者：

Kwentus, AY ^{[1
]}

Pai, P ^{[1
]}

Jaffe, S ^{[1
]}

Gomez, R ^{[1
]}

Tsai, S ^{[1
]}

Kwan, T ^{[1
]}

Hung, HT ^{[1
]}

Shin, YJ ^{[1
]}

Hue, V ^{[1
]}

Cheung, D ^{[1
]}

Khan, RA ^{[1
]}

Ward, CM ^{[1
]}

Ku, MK ^{[1
]}

Choi, K ^{[1
]}

Searle, J ^{[1
]}

Bult, K ^{[1
]}

Cameron, K ^{[1
]}

Demas, J ^{[1
]}

Reames, C ^{[1
]}

Samueli, H ^{[1
]}

机构：

[1] Broadcom Corp, Irvine, CA 92618 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1999年 / 34卷 / 11期

关键词：

Analog to digital conversion - CMOS integrated circuits - Data communication systems - Decoding - Demodulation - Digital filters - Error analysis - Error correction - Microprocessor chips - Quadrature phase shift keying - Signal receivers - Timing circuits;

D O I：

10.1109/4.799874

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a complete single-chip universal digital satellite receiver supporting all current DBS system standards. The mired-signal device accepts a modulated data stream at up to 90 Mbps and delivers a demodulated, error-corrected output data stream. The IC features an analog front end with 480-MHz intermediate-frequency downconversion and dual 8-bit analog-to-digital converters, an all-digital BPSK/QPSK/OQPSK variable-rate receiver supporting 1-45-MBaud operation with phase/frequency recovery, variable-rate digital filters, square-root Nyquist matched filters, acquisition and tracking loops, and a DVB/DSS/DigiCipher I/II-compliant concatenated Viterbi/Reed-Solomon forward error correction decoder with on-chip deinterleaver RAM. All required clocks are generated on chip from a single reference crystal. The chip contains 1.2 million transistors in a die area of 22 mm(2) and was implemented in a single-poly 0.35-mu m CMOS process with four layers of metal.

引用

页码：1634 / 1646

页数：13

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