Downsizing and Memory Array Integration of Pt/SrBi2Ta2O9/Hf-Al-O/Si Ferroelectric-Gate Field-Effect Transistors

被引:0
|
作者
Sakai, Shigeki [1 ]
Zhang, Xizhen [1 ]
Le Van Hai [1 ]
Zhang, Wei [1 ]
Takahashi, Mitsue [1 ]
机构
[1] Natl Inst Adv Ind Sci & Technol, 1-1-1 Umezono, Tsukuba, Ibaraki 3058568, Japan
关键词
ferroelectric; FeFET; Fe-NAND; flash memory; FILM;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
First, fabrication and characterization of a NAND flash memory using novel memory cells of ferroelectric-gate field-effect transistors (FeFETs), which is named Fe-NAND, was reviewed. A 64 kb Fe-NAND memory cell array with bit-line-and block-selector circuits was produced and characterized. Several standard operations for a NAND flash memory were demonstrated. All-cell-erase, all-cell-program, and a checkerboard-pattern program showed a good "1" vs. "0" separation in their threshold-voltage distributions. Downsizing of the memory-cell FeFETs has been also progressed. The FeFET with the gate-length 0.26 mu m showed high endurance by 109 cycles of 1 +/- 5 V-high and 10 mu s-wide pulses imposed. Second, we also discussed our FeFET performance in comparison with the other HfO2-based nonvolatile FETs.
引用
收藏
页码:55 / 59
页数:5
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