A Reduced-Bias Approach With a Lightweight Hard-Multiple Generator to Design a Radix-8 Modulo 2n+1 Multiplier

The modulo 2(n) + 1 multiplier is the bottleneck of a wide range of applications from residue number system arithmetic to cryptography. Recently, with demand for low-power and energy-efficient designs, the radix-8 Booth recoding has been considered to derive modulo 2(n) + 1 multipliers. This brief presents two novel methods to increase the performance and improve the efficiency of radix-8 modulo 2(n) + 1 multipliers. The first technique is a method to significantly reduce the amount of bias terms that need to be handled. The second technique is a new hard multiple generator based on a parallel-prefix structure that computes only for odd positions; it results in a lightweight parallel-prefix adder for the computation of the triple of a number with significant area-saving and improved fan-out. The implementation results based on the TSMC 65-nm technology show improvements of at least 27% and up to 57% in the area-time2 product when compared with the recently proposed radix-8 multiplier.