共 50 条
- [1] Efficient transient electrothermal simulation of CMOS VLSI circuits under electrical overstress [J]. 1998 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN: DIGEST OF TECHNICAL PAPERS, 1998, : 6 - 11
- [2] A chip-level electrothermal simulator for temperature profile estimation of CMOS VLSI chips [J]. ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 4, 1996, : 580 - 583
- [3] Electrothermal simulation of analogue integrated circuits with ETS [J]. THERMAL MANAGEMENT OF ELECTRONIC SYSTEMS II, 1997, : 83 - 92
- [4] FAULT SIMULATION IN CMOS VLSI CIRCUITS [J]. IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES, 1991, 138 (04): : 203 - 212
- [7] AN EXTENDED DIGITAL FAULT SIMULATOR FOR VLSI CIRCUITS [J]. IEICE TRANSACTIONS ON COMMUNICATIONS ELECTRONICS INFORMATION AND SYSTEMS, 1991, 74 (10): : 3051 - 3056
- [9] Delay analysis of UDSM CMOS VLSI circuits [J]. INTERNATIONAL CONFERENCE ON COMMUNICATION TECHNOLOGY AND SYSTEM DESIGN 2011, 2012, 30 : 135 - 143
- [10] Interconnect coupling noise in CMOS VLSI circuits [J]. Proceedings of the International Symposium on Physical Design, 1999, : 48 - 53