Low power design for MPEG-2 video decoder

被引：5

作者：

Lin, CH ^{[1
]}

Chen, CM ^{[1
]}

Jen, CW ^{[1
]}

机构：

[1] NATL CHIAO TUNG UNIV,INST ELECT,HSINCHU,TAIWAN

来源：

IEEE TRANSACTIONS ON CONSUMER ELECTRONICS | 1996年 / 42卷 / 03期

关键词：

D O I：

10.1109/30.536150

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The I/O power consumption in MPEG-2 decoder is significant because of the wide connection with large capacitances to the frame buffer. To reduce the power dissipation on the Memory Bus, the Gray code encoding scheme is proposed to increase the correlation of the image data transferred on the bus. The bit switching probability in the re-coded data will then decrease and in turn the bus power consumption will be reduced. Combined with the proposed bus arbitration and scheduling scheme proposed in this paper, 22% reduction of power dissipation may be achieved.

引用

页码：513 / 521

页数：9

共 50 条

[31] Wordlength optimization of an MPEG-2 audio decoder
Jeong, MS
Kim, S
Sohn, J
Sung, WY
[J]. APCCAS '96 - IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS '96, 1996, : 97 - 100
[32] A low-power variable length decoder for MPEG-2 based on successive decoding of short codewords
Lee, SW
Park, IC
[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 2003, 50 (02): : 73 - 82
[33] Application of a dynamically reconfigurable cell-array processor to an MPEG-2 video decoder
Komoku, K
Hatano, F
Morishita, T
Teramoto, I
[J]. RECONFIGURABLE TECHNOLOGY: FPGAS FOR COMPUTING AND APPLICATIONS II, 2000, 4212 : 42 - 49
[34] VLSI design of MPEG-2 video variable length decoding
Hui, Xinbiao
Zheng, Zhihang
Ye, Nan
[J]. Shanghai Jiaotong Daxue Xuebao/Journal of Shanghai Jiaotong University, 1999, 33 (09): : 1111 - 1113
[35] A pure-ASIC design approach for MPEG-2 AAC audio decoder
Tsai, TH
Liu, CN
Wang, YW
[J]. ICICS-PCM 2003, VOLS 1-3, PROCEEDINGS, 2003, : 1633 - 1636
[36] Exploring design space of parallel realizations: MPEG-2 decoder case study
Dwivedi, BK
Hoogerbrugge, J
Stravers, P
Balakrishnan, M
[J]. PROCEEDINGS OF THE NINTH INTERNATIONAL SYMPOSIUM ON HARDWARE/SOFTWARE CODESIGN, 2001, : 92 - 97
[37] SoC platform based design of MPEG-2/4 AAC audio decoder
Liu, CN
Tsai, TH
[J]. 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 2851 - 2854
[38] An MPEG-2 decoder case study as a driver for a system level design methodology
van der Wolf, P
Lieverse, P
Goel, M
La Hei, D
Vissers, K
[J]. PROCEEDINGS OF THE SEVENTH INTERNATIONAL WORKSHOP ON HARDWARE/SOFTWARE CODESIGN (CODES'99), 1999, : 33 - 37
[39] Super low delay operation demonstrated on MPEG-2 encoder and decoder modules
不详
[J]. MICROELECTRONICS INTERNATIONAL, 2004, 21 (01) : 46 - 46
[40] MPEG-2 AAC 5.1-Channel Decoder Software for a Low-Power Embedded RISC Microprocessor
Yuichiro Takamizawa
Kouhei Nadehara
Max Boegli
Masao Ikekawa
Ichiro Kuroda
[J]. Journal of VLSI signal processing systems for signal, image and video technology, 2001, 29 : 247 - 254

← 1 2 3 4 5 →