A three-stage load-balancing switch

被引：0

作者：

Wang, Xiaolin ^{[1
]}

Cai, Yan ^{[2
]}

Xiao, Sheng ^{[2
]}

Gong, Weibo ^{[2
]}

机构：

[1] Analog Devices Inc, Wilmington, MA 01887 USA

[2] Univ Massachusetts, Dept Elect & Comp Engn, Amherst, MA 01003 USA

来源：

27TH IEEE CONFERENCE ON COMPUTER COMMUNICATIONS (INFOCOM), VOLS 1-5 | 2008年

基金：

美国国家科学基金会;

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Recently there has been a great deal of interest in load-balancing switches due to their simple architecture and high brandwidth. In this paper we propose a three-stage load-balancing switch along with output load-balancing to address the mis-sequencing problem. We show that our proposed scheme provides a delay guarantee bounded by the delay of an OQ switch with the same input traffic plus a constant while achieving 100% throughput for admissible traffic with (sigma,rho)-upper constraint.

引用

页码：96 / 100

页数：5

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