Electromagnetic interference and digital circuits: An initial study of clock networks

被引:9
|
作者
Wang, HX [1 ]
Rodriguez, SV [1 ]
Dirik, C [1 ]
Jacob, B [1 ]
机构
[1] Univ Maryland, Dept Elect & Comp Engn, College Pk, MD 20742 USA
基金
美国国家科学基金会;
关键词
RFI; pin direct injection method; power reflection coefficient; pulsed modulated RF; clock network; metastability;
D O I
10.1080/02726340500214928
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Radio frequency interference (RFI) can have adverse effects on commercial electronics. Current properties of high-performance integrated circuits (ICs), such as very small feature sizes, high clock frequencies, and reduced voltage levels, increase the susceptibility of these circuits to RFI, causing them to be more prone to smaller RFI levels. Besides, recent developments of mobile devices and wireless networks create a hostile electromagnetic environment for ICs. Therefore, it is important to generalize the susceptibility of ICs to RFI. In this study, we investigate the susceptibility levels and frequency ranges of RFI to the clock network of a digital device, an 8-bit ripple counter, designed and fabricated using AMI 0.5 mu m process technology. Our experimental setup is designed to couple a pulse-modulated RF signal using the direct pin injection method. Our experiments show that relatively low levels of RFI (e. g., 16.8 dBm delivered RF peak power with carrier frequency of 1 GHz) could adversely affect the normal functioning of the device under testing. In the end, SPICE simulations show the sensitivity of a flip-flop, the basic building block of clock network, which further explains the experimental results.
引用
收藏
页码:73 / 86
页数:14
相关论文
共 50 条
  • [21] Integration of Clock Gating and Power Gating in Digital Circuits
    Rachel, Agnes Shiny N.
    Fahimunnisha, B.
    Akilandeswari, S.
    Venula, Joyes S.
    2019 5TH INTERNATIONAL CONFERENCE ON ADVANCED COMPUTING & COMMUNICATION SYSTEMS (ICACCS), 2019, : 704 - 707
  • [22] Digital Clock and Data Recovery Circuits for Optical Links
    Shu, Guanghua
    Choi, Woo-Seok
    Hanumolu, Pavan Kumar
    2016 IEEE COMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT SYMPOSIUM (CSICS), 2016, : 126 - 129
  • [23] The immunity of evolvable digital circuits to ESD interference
    Shanghe Liu
    Menghua Man
    Zhengquan Ju
    Xiaolong Chang
    Jie Chu
    Liang Yuan
    Journal of Bionic Engineering, 2012, 9 : 358 - 366
  • [24] A COMPARISON STUDY OF BINARY FEEDFORWARD NEURAL NETWORKS AND DIGITAL CIRCUITS
    ANDREE, HMA
    BARKEMA, GT
    LOURENS, W
    TAAL, A
    VERMEULEN, JC
    NEURAL NETWORKS, 1993, 6 (06) : 785 - 790
  • [25] CLOCK SYNCHRONIZATION SYSTEM FOR DIGITAL NETWORKS
    OKINO, T
    TSUDA, H
    HASHI, T
    FUJITSU SCIENTIFIC & TECHNICAL JOURNAL, 1985, 21 (01): : 67 - 80
  • [26] Reliable study of digital IC circuits with margin voltage among variable DC power supply, electromagnetic interference and conducting wire antenna
    Tsai, HC
    MICROELECTRONICS RELIABILITY, 2003, 43 (12) : 2001 - 2009
  • [27] The Immunity of Evolvable Digital Circuits to ESD Interference
    Liu, Shanghe
    Man, Menghua
    Ju, Zhengquan
    Chang, Xiaolong
    Chu, Jie
    Yuan, Liang
    JOURNAL OF BIONIC ENGINEERING, 2012, 9 (03) : 358 - 366
  • [28] DIGITAL-SIMULATION OF NONLINEAR ELECTROMAGNETIC CIRCUITS
    JONAS, G
    ELEKTROTECHNISCHE ZEITSCHRIFT B-AUSGABE, 1975, 27 (22): : 598 - 601
  • [29] Digital Simulation of Nonlinear Electromagnetic Circuits.
    Jonas, Georg
    Elektrotechnische Zeitschrift Ausgabe B, 1975, 27 (22): : 598 - 601
  • [30] Nonlinear Jitter of a Clock Path Due to Electromagnetic Interference on the Supply
    Huang, Zhuoquan
    Yang, Simei
    Su, Tao
    IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, 2018, 60 (01) : 243 - 251