Frequency Synthesizers for 5G Applications

被引:0
|
作者
Levantino, Salvatore [1 ]
机构
[1] Politecn Milan, Dipartimento Elettron Informaz Bioingn, Milan, Italy
关键词
TO-TIME CONVERTER; RANGE-REDUCTION TECHNIQUE; JITTER; PLL; FIGURE; MERIT;
D O I
10.1109/VLSI-SoC54400.2022.9939577
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Fifth-generation cellular transceivers operating in the millimeter-wave band require a local oscillator in the tens of gigahertz range, with an absolute jitter below 100 fs rms. In recent years, bang-bang digital and sampling analog phase-locked loops have been demonstrated to be the practical alternatives to conventional charge-pump ones, achieving lower jitter and power consumption in nanoscale CMOS processes. The adoption of those architectures in high-performance fractional-N frequency synthesis has been possibile with the assistance of digital-to-time converters which enable the cancellation of the divider quantization noise at the input of the phase-detection block.
引用
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页数:4
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