Real-time video surveillance on an embedded, programmable platform

被引:10
|
作者
Ngo, Hau T. [1 ]
Ives, Robert W. [1 ]
Rakvic, Ryan N. [1 ]
Broussard, Randy P. [2 ]
机构
[1] US Naval Acad, Dept Elect & Comp Engn, Annapolis, MD 21402 USA
[2] US Naval Acad, Weap & Syst Engn Dept, Annapolis, MD 21402 USA
关键词
Embedded systems; On-chip buffering scheme; Pipeline and parallel architecture; FPGA-based real-time video processing; Video surveillance; Object detection; FPGA;
D O I
10.1016/j.micpro.2013.06.003
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this work, a hardware-software co-design is proposed to effectively utilize FPGA resources for a prototype of an automated video surveillance system on a programmable platform. Time-critical steps of a foreground object detection algorithm are designed and implemented in the FPGA's logic elements to maximize parallel processing. Other non time-critical tasks are achieved by executing a high level language program on an embedded Nios-II processor. Custom and parallel processing modules are integrated into the video processing chain by a streaming protocol that aggressively utilizes on-chip memory to increase the throughput of the system. A data forwarding technique is incorporated with an on-chip buffering scheme to reduce computations and resources in the window-based operations. Other data control interfaces are achieved by software drivers that communicate with hardware controllers using Altera's Memory-Mapped protocol. The proposed prototype has demonstrated real-time processing capability that outperforms other implementations. Published by Elsevier B.V.
引用
收藏
页码:562 / 571
页数:10
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