Low-Power Bulk-Driven Rail-to-Rail Comparator in 130 nm CMOS Technology

This paper addresses a design and performance evaluation of a non-clocked comparator circuit intended to work in a wide temperature range with very low value of the power supply voltage. Due to low voltage swing, the input voltage range is set to be rail-to-rail. The target fabrication process is a standard twin-well 130 nm CMOS technology, with appropriate parameters required to meet circuit specifications. The nominal power supply voltage for this technology has been halved to the value of 0.6 V. However, the proposed circuit topology is able to work with even lower supply voltage. The comparator was designed employing g(m)/I-D methodology along with bulk-driven transistors. The post-layout simulations have been carried out in order to evaluate the circuit performance in all process and temperature corners as well as by means of Monte-Carlo analysis. Very promising results have been obtained and the proposed comparator was successfully employed in a charge pump system.