Low Complexity Implementation of Slim - HEVC Encoder Design

High efficiency video coding (HEVC) is the most recently standardized video codec that was completed in January 2013. HEVC standard can achieve about 50 percent of average bit-rate reduction compared to H.264/advanced video coding (AVC) so it can show higher coding efficiency and higher resolution. Although each function in HEVC is similar to previous standard, there are a lot of improvements in respective functions such as prediction methods, block based transform coding, filtering and so on. As HEVC shows better performance than prior video codec standard, it has more complexity issues. Especially, newly added prediction method in inter and intra prediction and improved cost computing method can show high coding performance in software, but the hardware cost becomes very high. In this paper, we focus on its huge complexity and propose low complexity encoder model which is based on high efficiency video codec exhaustive. The proposed slim - HEVC encoder is compliant with HM 10.0 which is developed during standardization of HEVC so that it is consisted of inter and intra prediction modes, in-loop filter and context-based adaptive binary arithmetic (CABAC). Although several functions in HEVC standard are removed, it can make about 1.5 times better performance rather than H.264/AVC. Working frequency of the proposed slim - HEVC encoder is 200MHz when full HD (Full High Definition, 1920x1080) resolution sized video encoded. All of our design has been implemented in Verilog RTL.