Energy Aware Scheduling and Dynamic Job Mapping Algorithm for Network-on-Chip Architectures

被引:0
|
作者
Kalaivani, J. [1 ]
Vinayagasundaram, B. [1 ]
机构
[1] Anna Univ, Madras Inst Technol, IT Dept, Madras, Tamil Nadu, India
来源
2016 5TH INTERNATIONAL CONFERENCE ON RECENT TRENDS IN INFORMATION TECHNOLOGY (ICRTIT) | 2016年
关键词
Task scheduling; dynamic job mapping;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
The routing results of Network-on-Chip (NoC) increase energy consumption and delay. In order to overcome this issue, Energy aware task scheduling followed by dynamic job mapping concept is developed for NoC. Energy aware task scheduling algorithm allocates tasks on different elements under process and schedules the execution. Dynamic task mapping is applied to improve the performance of NoC and also to reduce both power consumption and delay in a non-preemptive network. The result of this proposed technique is more energy efficient and reduces latency.
引用
收藏
页数:4
相关论文
共 50 条
  • [1] An Energy-Aware Mapping Algorithm for Mesh-based Network-on-Chip Architectures
    Sun, Jin
    Zhang, Yi
    PROCEEDINGS OF 2017 IEEE INTERNATIONAL CONFERENCE ON PROGRESS IN INFORMATICS AND COMPUTING (PIC 2017), 2017, : 357 - 361
  • [2] Energy- and Traffic-Balance-Aware Mapping Algorithm for Network-on-Chip
    Deng, Zhi
    Gu, Huaxi
    Yang, Yingtang
    You, Him
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2013, E96D (03) : 719 - 722
  • [3] Deadline and energy aware dynamic task mapping and scheduling for Network-on-Chip based multi-core platform
    Chatterjee, Navonil
    Paul, Suraj
    Mukherjee, Priyajit
    Chattopadhyay, Santanu
    JOURNAL OF SYSTEMS ARCHITECTURE, 2017, 74 : 61 - 77
  • [4] Contention-aware Application Mapping for Network-on-Chip Communication Architectures
    Chou, Chen-Ling
    Marculescu, Radu
    2008 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, 2008, : 164 - 169
  • [5] BARR: Congestion aware scheduling algorithm for Network-on-Chip router
    Su, Nan
    Wang, Kun
    Yu, Xiaoshan
    Gu, Huaxi
    Guo, Yantao
    Chen, Jiayi
    IEICE ELECTRONICS EXPRESS, 2017, 14 (03):
  • [6] Integrated mapping and scheduling for circuit-switched network-on-chip architectures
    Chi, Hsin-Chou
    Wu, Chia-Ming
    Lee, Jun-Hui
    DELTA 2008: FOURTH IEEE INTERNATIONAL SYMPOSIUM ON ELECTRONIC DESIGN, TEST AND APPLICATIONS, PROCEEDINGS, 2008, : 415 - 420
  • [7] A technique for low energy mapping and routing in network-on-chip architectures
    Srinivasan, K
    Chatha, KS
    ISLPED '05: PROCEEDINGS OF THE 2005 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2005, : 387 - 392
  • [8] Cost Aware Task Scheduling And Core Mapping on Network-on-Chip topology using Firefly Algorithm
    Umamaheswari, S.
    Kirthiga, Indu K.
    Abinaya, B. S.
    Ashwin, D.
    2013 INTERNATIONAL CONFERENCE ON RECENT TRENDS IN INFORMATION TECHNOLOGY (ICRTIT), 2013, : 657 - 662
  • [9] Dynamic Application Mapping Algorithm for Wireless Network-on-Chip
    Rezaei, Amin
    Daneshtalab, Masoud
    Zhao, Danella
    Safaei, Farshad
    Wang, Xiaohang
    Ebrahimi, Masoumeh
    23RD EUROMICRO INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED, AND NETWORK-BASED PROCESSING (PDP 2015), 2015, : 421 - 424
  • [10] Deadline-Aware and Energy-Efficient Dynamic Task Mapping and Scheduling for Multicore Systems Based on Wireless Network-on-Chip
    Dehghani, Abbas
    Fadaei, Sadegh
    Ravaei, Bahman
    Rahimizadeh, Keyvan
    IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING, 2023, 11 (04) : 1031 - 1044