Low-power-consumption 10-Gbps GaAs 8:1 multiplexer 1:8 demultiplexer

被引：2
|
作者：
Yoshida, N
Fujii, M
Atsumo, T
Numata, K
Asai, S
Kohno, M
Oikawa, H
Tsutsui, H
Maeda, T
机构：
来源：
GAAS IC SYMPOSIUM - 19TH ANNUAL, TECHNICAL DIGEST 1997 | 1997年
关键词：
D O I：
10.1109/GAAS.1997.628250
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An ECL-compatible 10-Gbps GaAs 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) has been developed. To decrease power consumption and to maximize phase margin, the clock-generating circuit employs source-coupled PET logic (SCFL) circuits. Also, cascade-connected source-follower circuits are used in the clock buffer. These circuits can reduce the power consumption when the fan-out number is large. Direct coupled FET logic (DCFL) circuits are employed for the 2:1 MUX/1:2 DEMUX circuits operating below 5 Gbps. The ICs, which are mounted on ceramic packages, operate at up to 10 Gbps with a power consumption of 1.2 W for the MUX and 1.0 W for the DEMUX at ECL-compatible supply voltages. These power-consumption values are one-third of the previously reported values.
引用
收藏
页码：113 / 116
页数：4
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