Cost-efficient SHA hardware accelerators

被引：40

作者：

Chaves, Ricardo ^{[1
,2
]}

Kuzmanov, Georgi ^{[2
]}

Sousa, Leonel ^{[1
]}

Vassiliadis, Starnatis ^{[2
]}

机构：

[1] Inst Super Tecn INESC ID, P-1049001 Lisbon, Portugal

[2] Delft Univ Technol, Dept Comp Engn, EEMCS, NL-2628 CD Delft, Netherlands

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2008年 / 16卷 / 08期

关键词：

crytography; field-programmable gate array (FPGA); hardware implementation; hash functions; Secure Hash Algorithm (SHA);

D O I：

10.1109/TVLSI.2008.2000450

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a new set of techniques for hardware implementations of Secure Hash Algorithm (SHA) hash functions. These techniques consist mostly in operation rescheduling and hardware reutilization, therefore, significantly decreasing the critical path and required area. Throughputs from 1.3 Gbit/s to 1.8 Gbit/s were obtained for the SHA implementations on a Xilinx VIRTEX II Pro. Compared to commercial cores and previously published research, these figures correspond to an improvement in throughput/slice in the range of 29% to 59% for SHA-1 and 54% to 100% for SHA-2. Experimental results on hybrid hardware/software implementations of the SHA cores, have shown speedups up to 150 times for the proposed cores, compared to pure software implementations.

引用

页码：999 / 1008

页数：10

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