SERL: Soft Error Resilient Latch Design

被引：0

作者：

Chang, Chun-Wei ^{[1
]}

Huang, Hsuan-Ming ^{[1
]}

Lin, Yuwen ^{[1
]}

Wen, Charles H. -P. ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Dept Elect & Comp Engn, Hsinchu 300, Taiwan

来源：

2016 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT) | 2016年

关键词：

SER; BISER; SEU; SET;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Soft errors, radiation-induced transient faults latched by memory elements, have emerged to be one dominant failure mechanism for scaled CMOS designs. Therefore, this paper presents a robust design named soft error resilient latch (SERL). Compared to BISER, one of the latest latch designs, SERL demonstrates better soft error protection with smaller area overhead.

引用

页数：4

共 50 条

[1] A New Soft-Error Resilient Voltage-Mode Quaternary Latch
Rhod, Eduardo
Sterpone, Luca
Carro, Luigi
[J]. 2010 IEEE 25TH INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS (DFT 2010), 2010, : 200 - 208
[2] Soft error resilient system design through error correction
Mitra, Subhasish
Zhang, Ming
Seifert, Norbert
Mak, T. M.
Kim, Kee Sup
[J]. VLSI-SOC: RESEARCH TRENDS IN VLSI AND SYSTEMS ON CHIP, 2008, : 143 - +
[3] Soft error resilient system design through error correction
Mitra, Subhasish
Zhang, Ming
Seifert, Norbert
Mak, T. M.
Kim, Kee Sup
[J]. IFIP VLSI-SOC 2006: IFIP WG 10.5 INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION & SYSTEM-ON-CHIP, 2006, : 332 - +
[4] Soft Error Immune Latch Design for 20 nm bulk CMOS
Uemura, Taiki
Kato, Takashi
Matsuyama, Hideya
Hashimoto, Masanori
[J]. 2015 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2015,
[5] Soft Error Tolerant Latch Design with Low Cost for Nanoelectronic Systems
Nan, Haiqing
Choi, Ken
[J]. 2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), 2012, : 1572 - 1575
[6] Soft Error Filtered and Hardened Latch
Alidash, Hossein Karimiyan
Sayedi, Sayed Masoud
Saidi, Hossein
Oklobdzija, Vojin G.
[J]. 2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2009, : 613 - +
[7] A Soft Error Resilient Low Leakage SRAM Cell Design
Adithyalal, P. M.
Balachandran, Shankar
Singh, Virendra
[J]. 2015 IEEE 24TH ASIAN TEST SYMPOSIUM (ATS), 2015, : 133 - 138
[8] Design Framework for Soft-Error-Resilient Sequential Cells
Lee, Hsiao-Heng Kelin
Lilja, Klas
Bounasser, Mounaim
Linscott, Ivan
Inan, Umran
[J]. IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2011, 58 (06) : 3026 - 3032
[9] A Novel Soft Error Hardened Latch Design in 90nm CMOS
Shirinzadeh, Saeideh
Asli, Rahebeh Niaraki
[J]. 2012 16TH CSI INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SYSTEMS (CADS), 2012, : 60 - 63
[10] A Power-Efficient Soft Error Hardened Latch Design with In-Situ Error Detection Capability
Tajima, Saki
Yanagisawa, Masao
Shi, Youhua
[J]. 2019 IEEE ASIA PACIFIC CONFERENCE ON POSTGRADUATE RESEARCH IN MICROELECTRONICS AND ELECTRONICS (PRIMEASIA 2019): INNOVATIVE CAS TOWARDS SUSTAINABLE ENERGY AND TECHNOLOGY DISRUPTION, 2019, : 53 - 56

← 1 2 3 4 5 →