Design Framework for Soft-Error-Resilient Sequential Cells

被引：29

作者：

Lee, Hsiao-Heng Kelin ^{[1
,2
]}

Lilja, Klas ^{[3
]}

Bounasser, Mounaim ^{[3
]}

Linscott, Ivan ^{[4
]}

Inan, Umran ^{[4
,5
]}

机构：

[1] VLF Grp, Stanford, CA 94305 USA

[2] Stanford Univ, Robust Syst Grp, Dept Elect Engn, Stanford, CA 94305 USA

[3] Robust Chip Inc, Pleasanton, CA 94588 USA

[4] Stanford Univ, Dept Elect Engn, VLF Grp, Stanford, CA 94305 USA

[5] Koc Univ, Istanbul, Turkey

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 2011年 / 58卷 / 06期

关键词：

CMOS integrated circuits; DICE; LEAP; radiation hardening; sequential circuits; soft error; GATES;

D O I：

10.1109/TNS.2011.2168611

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a design framework for soft-error-resilient sequential cells, by introducing a new sequential cell called LEAP-DICE and evaluating it against existing circuit techniques in the "soft error resilience-power-delay-area" design space in an 180 nm CMOS test chip. LEAP-DICE, which employs both circuit and layout techniques, achieved the best soft error performance with a 2,000X improvement over the reference D flip-flop with moderate design costs. This study also discovered new soft error effects related to operating conditions.

引用

页码：3026 / 3032

页数：7

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