共 50 条
- [1] Towards a high-level synthesis of reconfigurable bit-serial architectures 16TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, SBCCI 2003, PROCEEDINGS, 2003, : 79 - 84
- [2] A Design-flow for High-Level Synthesis and Resource Estimation of Reconfigurable Architectures 2015 10TH IEEE INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA (DTIS), 2015,
- [3] High-level Programming of Coarse-Grained Reconfigurable Architectures FPL: 2009 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, 2009, : 713 - 714
- [4] Verification of scheduling in high-level synthesis IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: EMERGING VLSI TECHNOLOGIES AND ARCHITECTURES, 2006, : 141 - +
- [5] A Survey of Verification for High-level Synthesis 1600, Institute of Computing Technology (33): : 287 - 297
- [6] Formal Verification of High-Level Synthesis PROCEEDINGS OF THE ACM ON PROGRAMMING LANGUAGES-PACMPL, 2021, 5 (OOPSLA):
- [9] Design and Verification Using High-Level Synthesis 2016 21ST ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2016, : 198 - 203
- [10] High-level Debugging And Verification For FPGA-Based Multicore Architectures 2015 IEEE 23RD ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM), 2015, : 135 - 142