Evaluation of a Declarative Linux Kernel FPGA Manager for Dynamic Partial Reconfiguration

Heterogeneous Multi-Processor Systems-on-Chip, whether ARM or x86 based, promise further performance scala-bility by complementing temporal compute in CPUs/GPUs with spatial compute in digital circuitry. Dynamic partial reconfiguration (DPR) extends such compute architectures by making use of different spatial compute elements over time. Novel research [1] presents means for operating DPR by the Linux kernel via so-called device tree overlays (DTOs) and, thereby, opens up FPGA-based acceleration for general purpose computing (GPC). Operating systems (OSs) for General Purpose Computing need to administer these reconfigurable FPGA resources and, thus, need metrics for handling the trade-offs between performance gains by acceleration, FPGA resource requirements, and turn-around-times within DPR context switches. Unfortunately, precise parameters for these metrics cannot be derived by theoretical analyses but only by experimental results. Based on exemplary implementations of programmable accelerators for the Linux Kernel Crypto-API, implemented on the Xilinx Zynq 7000 platform, we are able to present first OS metrics for DTO-based DPR. These metrics can guide future research on OSs for GPC on FPGAs.