470MHz digital filter on delta-sigma modulated signals

This paper describes a digital filter operating on Delta-Sigma modulated signals. Using a simple processor core comprising an ALU and multiple registers, controlled by an instruction ROM, this circuit operates at 470Mhz in 0.8 mu m CMOS. Novel features include partial carry propagation, which reduces circuit delay to that of a single carry-save adder, but results in inexact quantization. On-chip clocking synchronizes low-speed I/O signals to the internal 470Mhz clock. AII-N TSPC and conventional TSPC result in high clock speed of 470MHz in a 0.8 mu m process.