Performance Driven VLSI Floorplanning with B*Tree Representation Using Differential Evolutionary Algorithm

In this paper, we present a floorplanning algorithm based on B *Tree representation. Our floorplanner has explicitly designed for fixed-frame floorplanning, which is different from traditional minarea floorplanning. Moreover, we also show that it can be adapted to minimize total area. It addresses the problem of handling alignment constraint which arises in bus structure. It deals with performance constraint such as bounded net delay, while many existing floorplanners just minimize total wire length. More importantly, even with all these constraints the Differential evolutionary algorithm (DE) is very fast in the sense that it can quickly produce optimal solutions. Experimental results based on MCNC benchmark with constraints show that Differential Evolutionary (DE) can quickly produce optimal solutions.