Design of evolvable hardware using adaptive simulated annealing

被引：0
|
作者：
He, GL [1 ]
Li, YX [1 ]
Liu, F [1 ]
机构：
[1] Wuhan Univ, Sch Comp, Wuhan 430072, Hubei, Peoples R China
来源：
2005 INTERNATIONAL CONFERENCE ON WIRELESS COMMUNICATIONS, NETWORKING AND MOBILE COMPUTING PROCEEDINGS, VOLS 1 AND 2 | 2005年
关键词：
combinational logic circuit; evolvable hardware; simulated annealing;
D O I：
暂无
中图分类号：
TN [电子技术、通信技术];
学科分类号：
0809 ;
摘要：
The evolvable hardware technique is based on evolving the functionality and connectivity of a rectangular array of logic cells. In this paper, an adaptive simulated annealing algorithm is proposed for design combinational circuits with 100% functionality and minimized number of gates. Experiments for five combinational circuits with our method are compared with NGA, MGA, MLCEA and human designs produced by Karnaugh Maps and Quine-McCluskey method. Results show our method can optimize combinational circuits with shorter chromosome structure and is more adaptive for Evolvable Hardware.
引用
收藏
页码：1390 / 1392
页数：3
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