Low power ACS unit design for the Viterbi Decoder

被引：0

作者：

Tsui, CY ^{[1
]}

Cheng, RSK ^{[1
]}

Ling, C ^{[1
]}

机构：

[1] Hong Kong Univ Sci & Technol, Dept Elect & Elect Engn, Hong Kong, Peoples R China

来源：

ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1: VLSI | 1999年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we address the issues of designing low power VLSI implementation of the Viterbi Decoder. We propose a new VLSI architecture for carrying out the Add-Compare-Select (ACS) operation for the Viterbi decoder which can reduce the complexity of the computation. Also a novel pre-computational architecture is proposed to further reduce the power consumption of the ACS unit.

引用

页码：137 / 140

页数：4

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