High-performance ASIC implementations of the 128-bit block cipher CLEFIA

被引：0

作者：

Sugawara, Takeshi ^{[1
]}

Homma, Naofumi ^{[1
]}

Aoki, Takafumi ^{[1
]}

Satoh, Akashi ^{[2
]}

机构：

[1] Tohoku Univ, Grad Sch Informat Sci, Sendai, Miyagi 980, Japan

[2] Natl Inst Adv Ind Sci & Technol, Res Ctr Informat Secur, Tokyo 101, Japan

来源：

PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10 | 2008年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In the present paper, we introduce high-performance hardware architectures for the 128-bit block cipher CLEFIA and evaluate their ASIC performances in comparison with the ISO/IEC 18033-3 standard block ciphers (AES, Camellia, SEED, CAST-128, MISTY1, and TDEA). We designed five types of hardware architectures for CLEFIA, combining two loop structures and three F-functions. These designs were synthesized with a 90-nm CMOS standard cell library, and size and speed performances were evaluated. The highest hardware efficiency (defined as throughput/gates) obtained was 400.96 Kbps/gates, which is 1.5 times higher than previously achieved efficiencies.

引用

页码：2925 / +

页数：2

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