A highly efficient FPGA implementation of AES for high throughput IoT applications

With nearly 500 billion connected devices in 2025, information security will be the main concern of the researchers. It is the driving force in developing resource efficient cryptographic solutions. In this paper, we present a high throughput AES design with 32-bit data path that achieves the high efficiency via FPGA implementation. With the help of data path compression and effective utilization of FPGA architecture, the resource consumption is minimized. Galois field arithmetic is utilized for s-box implementation. Separate S-box for key generation has been employed to achieve higher throughput and low latency. The proposed design has been synthesized by PlanAhead software and implemented on different Xilinx FPGAs. It is compared with AES implementations. With a throughput of 2.34 Gbps and efficiency of 5.10 Mbps/slice, the design outperforms different lightweight ciphers. High throughput and low latency make it suitable for surveillance applications in IoT and smart grid.