Minimizationof Wirelength in 3d IC Routing By Using Differential Evolution Algorithm

被引：0
|
作者：
Pandiaraj, K. [1 ]
Sivakumar, P. [1 ]
Sridevi, R. [1 ]
机构：
[1] Kalasalingam Univ, Elect & Commun Engn Dept, Virudunagar 626126, Tamil Nadu, India
来源：
2017 IEEE INTERNATIONAL CONFERENCE ON ELECTRICAL, INSTRUMENTATION AND COMMUNICATION ENGINEERING (ICEICE) | 2017年
关键词：
Global Routing; 3D IC; Wire length;
D O I：
暂无
中图分类号：
TP39 [计算机的应用];
学科分类号：
081203 ; 0835 ;
摘要：
The wire-length of vertically stacked ICs plays a vital role. The wire-length is minimized by using differential evolutionary algorithms withIBM Benchmark inputs. Moreover this wire length is minimized with the respect to the length of the Through Silicon via (TSVs). As a result, the wire-length has been minimized using this algorithm with various parameters. Experimental result shows that the total wirelength can be reduced.
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页数：5
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