Carry save adder and carry look ahead adder using inverter chain based coplanar QCA full adder for low energy dissipation

Quantum-dot cellular automata (QCA) technology offers the potential option for performing transistor-less calculations at the nanoscale. In this paper, we introduce a new full adder structure using an inverter chain on a single layer. By utilizing the proposed full adder structure, we design and implement a carry save adder and carry look-ahead adder. Some of these techniques like pipeline structures or asynchronous timing becoming more attractive and are gaining more attention than other solutions. This paper mainly focuses on the high circuit density and energy-efficient aspects of QCA circuits. The design exploits the inherent pipeline nature of QCA, which can lead to an enormous reduction in area using an inverter chain since all computations can be computed in a single block. A comparison among our results and typical structures shows that the presented structures outperformed the best existing designs with respect to area, latency, and cell count. Our structures are more suitable elements for realizing complex QCA circuits with very high operating speed. Functional verification and energy consumption analyses were conducted by well known tools.