Analytical Model of a Multi-Resolution Sample rate re-configurable Decimator for SDADC

被引:0
|
作者
Mondal, Annapurna [1 ]
Bhar, Sagnik [1 ]
Srimani, Supriyo [1 ]
Hatai, Indranil [2 ]
Ghosh, Kasturi [1 ]
Rahaman, Hafizur [1 ]
机构
[1] IIEST, Sch VLSI Technol, Sibpur, Howrah, India
[2] Natl Univ Singapore, Elect & Comp Engn, Singapore, Singapore
来源
PROCEEDINGS OF 2019 IEEE REGION 10 SYMPOSIUM (TENSYMP) | 2019年
关键词
Sigma Delta ADC; Modulator; CIC Filter; Decimator; Decimation Factor; FILTERS;
D O I
10.1109/tensymp46218.2019.8971138
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
In biomedical applications, a sigma-delta analog-to-digital converter (SDADC), due to its high resolution, is very important in data acquisition systems. A decimator is used in SDADC to control the output sample rate. It also acts as a low pass filter and attenuates the out of band-shaped noise from the modulator output. It thus provides control over the effective resolution at the converter output. In this work, a re-configurable decimator has been proposed which will meet the design specifications for different biomedical signals like ECG, EEG, EMG and AED. The proposed architecture is simulated in MATLAB environment. The simulated results show that the proposed design can support the variation of sample rate from 1-32 KSPS, the resolution from 6-28 hit with the external over-sampling frequency range of 64 KHz-2.048 MHz.
引用
收藏
页码:588 / 592
页数:5
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