On improving a fault simulation based test generator for synchronous sequential circuits

被引：4
|
作者：
Guo, RF [1 ]
Reddy, SM [1 ]
Pomeranz, I [1 ]
机构：
[1] Intel Corp, Hillsboro, OR 97124 USA
来源：
10TH ASIAN TEST SYMPOSIUM, PROCEEDINGS | 2001年
关键词：
D O I：
10.1109/ATS.2001.990264
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We propose several techniques to improve a simulation based test pattern generation procedure for sequential circuits. The effectiveness of the proposed techniques is demonstrated through experimental results on a large set of benchmark circuits.
引用
收藏
页码：82 / 87
页数：6
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