Strengthening SPN-type block cipher architecture against fault attack

被引：0

作者：

Das, Satyajit ^{[1
]}

Bhaumik, Jaydeb ^{[2
]}

机构：

[1] CRRAO AIMSCS, Hyderabad, Andhra Pradesh, India

[2] Haldia Inst Technol, Dept Elect & Commun Engn, Kolkata, India

来源：

PROCEEDINGS OF THE 2012 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, DEVICES AND INTELLIGENT SYSTEMS (CODLS) | 2012年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

In this paper a Substitution Permutation Network(SPN) type, symmetric-key block cipher architecture has been proposed to strengthen it against fault attack. The proposed SPN type architechture employes two different types of diffusion layers. Each odd round contains eight parallel 16 bits diffusion layer and each even round contains two parallel 64 bits diffusion layer. Our architecture has been implemented in Spartan-3 FPGA xc3s5000 device and it provides a acceptable throughput of 866.538 Mbps. In this work, first time two different types of diffusion layer are used to strengthen SPN-type block cipher architecture against fault attack.

引用

页码：560 / 563

页数：4

共 43 条

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[J]. IEEE ACCESS, 2022, 10 : 67802 - 67813
[42] Design and Evaluation of Countermeasures Against Fault Injection Attacks and Power Side-Channel Leakage Exploration for AES Block Cipher
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TENA-SANCHEZ, E.
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JIMENEZ-FERNANDEZ, C. J.
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[J]. IEEE ACCESS, 2022, 10 : 65548 - 65561
[43] An In-Depth Vulnerability Analysis of RISC-V Micro-Architecture Against Fault Injection Attack
Kazemi, Zahra
Norollah, Amin
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Fazeli, Mahdi
Hely, David
Beroulle, Vincent
[J]. 34TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFT 2021), 2021,

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