The Synthesis of Cyclic Dependencies with Boolean Satisfiability

被引:7
|
作者
Backes, John D. [1 ]
Riedel, Marc D. [1 ]
机构
[1] Univ Minnesota, Dept Elect & Comp Engn, Minneapolis, MN 55455 USA
关键词
Algorithms; Theory; Verification; Boolean satisfiability; circuit verification; cyclic circuits; logic design; logic synthesis; INTERPOLATION;
D O I
10.1145/2348839.2348848
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The accepted wisdom is that combinational circuits must have acyclic (i.e., feed-forward) topologies. Yet simple examples suggest that this is incorrect. In fact, introducing cycles (i.e., feedback) into combinational designs can lead to significant savings in area and in delay. Prior work described methodologies for synthesizing cyclic circuits with Sum-Of-Product (SOP) and Binary-Decision Diagram (BDD)-based formulations. Recently, techniques for analyzing and mapping cyclic circuits based on Boolean satisfiability (SAT) were proposed. This article presents a SAT-based methodology for synthesizing cyclic dependencies. The strategy is to generate cyclic functional dependencies through a technique called Craig interpolation. Given a choice of different functional dependencies, a branch-and-bound search is performed to pick the best one. Experiments on benchmark circuits demonstrate the effectiveness of the approach.
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页数:24
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