45nm high-k plus metal gate strain-enhanced transistors

被引：0

作者：

Auth, C. ^{[1
]}

Cappellani, A. ^{[1
]}

Chun, J. -S. ^{[1
]}

Dalis, A. ^{[1
]}

Davis, A. ^{[1
]}

Ghani, T. ^{[1
]}

Glass, G. ^{[1
]}

Glassman, T. ^{[1
]}

Harper, M. ^{[1
]}

Hattendorf, M. ^{[1
]}

Hentges, P. ^{[1
]}

Jaloviar, S. ^{[1
]}

Joshi, S. ^{[1
]}

Klaus, J. ^{[1
]}

Kuhn, K. ^{[1
]}

Lavric, D. ^{[1
]}

Lu, M. ^{[1
]}

Mariappan, H. ^{[1
]}

Mistry, K. ^{[1
]}

Norris, B. ^{[1
]}

Rahhal-orabi, N. ^{[1
]}

Ranade, P. ^{[1
]}

Sandford, J. ^{[1
]}

Shifren, L. ^{[1
]}

Souw, V. ^{[1
]}

Tone, K. ^{[1
]}

Tambwe, F. ^{[1
]}

Thompson, A. ^{[1
]}

Towner, D. ^{[1
]}

Troeger, T. ^{[1
]}

Vandervoom, P. ^{[1
]}

Wallace, C. ^{[1
]}

Wiedemer, J. ^{[1
]}

Wiegand, C. ^{[1
]}

机构：

[1] Intel Corp, Log Technol Dev, Hillsboro, OR 97124 USA

来源：

2008 SYMPOSIUM ON VLSI TECHNOLOGY | 2008年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Two key process features that are used to make 45nm generation metal gate + high-k gate dielectric CMOS transistors are highlighted in this paper. The first feature is the integration of stress-enhancement techniques with the dual metal-gate + high-k transistors. The second feature is the extension of 193nm dry lithography to the 45nm technology node pitches. Use of these features has enabled industry-leading transistor performance and the first high volume 45nm high-k + metal gate technology.

引用

页码：99 / +

页数：2

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