Evaluation of architectural support for global address-based communication in large-scale parallel machines

被引：0

作者：

Krishnamurthy, A ^{[1
]}

Schauser, KE ^{[1
]}

Scheiman, CJ ^{[1
]}

Wang, RY ^{[1
]}

Culler, DE ^{[1
]}

Yelick, K ^{[1
]}

机构：

[1] UNIV CALIF SANTA BARBARA,DEPT COMP SCI,SANTA BARBARA,CA 93106

来源：

ACM SIGPLAN NOTICES | 1996年 / 31卷 / 09期

关键词：

D O I：

10.1145/248209.237147

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

Large-scale parallel machines are incorporating increasingly sophisticated architectural support for user-level messaging and global memory access. We provide a systematic evaluation of a broad spectrum of current design alternatives based on our implementations of a global address language on the Thinking Machines CM-5, Intel Paragon, Meiko CS-2, Gray T3D, and Berkeley NOW. This evaluation includes a range of compilation strategies that make varying use of the network processor; each is optimized for the target architecture and the particular strategy. We analyze a family of interacting issues that determine the performance tradeoffs in each implementation, quantify the resulting latency, overhead, and bandwidth of the global access operations, and demonstrate the effects on application performance.

引用

页码：37 / 48

页数：12

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