A time-constant calibrated phase-locked loop with a fast-locked time

被引：5

作者：

Han, Sung-Rung ^{[1
]}

Chuang, Chi-Nan

Liu, Shen-Iuan

机构：

[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10617, Taiwan

[2] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2007年 / 54卷 / 01期

关键词：

fast locked; phase-locked loop (PLL); time-constant calibration; variable capacitance multiplier (VCM);

D O I：

10.1109/TCSII.2006.883826

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A time-constant calibrated phase-locked loop with a fast-locked time is presented. A variable capacitance multiplier (VCM) is developed to adjust the equivalent capacitance in the loop filter. And a calibration circuit is used to allow the time constant of the loop filter to track with the reference clock. By using the proposed time-constant calibration circuit and the VCM, the fast acquisition time is achieved and the loop capacitance is also multiplied. A prototype has been fabricated in a 0.35-mu m CMOS process to demonstrate the proposed circuit.

引用

页码：34 / 37

页数：4

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