Automatic fault diagnosis for scan-based designs

被引:0
|
作者
Heinitz, M
Hollenbeck, I
Kuboschek, M
Otterstedt, J
Sebeke, C
Winkel, T
机构
[1] Inst. für Theor. Elektrotechnik, Universität Hannover, D-30167 Hannover
[2] Lab. fur Informationstechnologie, Universität Hannover, D-30167 Hannover
关键词
Number:; OMI/DE-ARM; 6909; Acronym:; -; Sponsor:;
D O I
10.1016/0167-9317(95)00355-X
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This contribution presents an automatic fault diagnosis system which is designed to combinational circuits and circuit modules embedded in a scan path environment. It consists of a diagnosis software called DIABOLO (DIAgnosis of BOolean LOgic), an electron beam tester (EBT) and a digital tester. A novel concept for a complete automatic fault diagnosis process is proposed: The applied test patterns and test sequences are specifically generated for the fault diagnosis of scan-based circuits with support of the EBT. This approach allows the drastic reduction of EBT measurement times respectively the reduction of the number of internal circuit nodes which have to be observed by the EBT. Each step of the fault diagnosis process has certain requirements for the applied test patterns and test sequences. Therefore, different types of test patterns and sequences are applied during one diagnosis run, for example, inherently periodical test patterns [1], diagnostic test patterns [2] and short test sequences are employed [3]. The test pattern / sequence generation is performed automatically (which is the prerequisite for automatic fault diagnosis) and online, that is it depends on the predecessing results of the actual fault diagnosis process. Experiments demonstrate the feasibility of the proposed concept.
引用
下载
收藏
页码:331 / 338
页数:8
相关论文
共 50 条
  • [21] Static test compaction for scan-based designs to reduce test application time
    Pomeranz, I
    Reddy, SM
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2000, 16 (05): : 541 - 552
  • [22] Is state mapping essential for equivalence checking custom memories in scan-based designs?
    Krishnamurthy, N
    Bhadra, J
    Abadir, MS
    Abraham, JA
    20TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2002, : 275 - 280
  • [23] Static Test Compaction for Scan-Based Designs to Reduce Test Application Time
    Irith Pomeranz
    Sudhakar M. Reddy
    Journal of Electronic Testing, 2000, 16 : 541 - 552
  • [24] Scan-based transition fault testing - Implementation and low cost test challenges
    Saxena, J
    Butler, KM
    Gatt, J
    Raghuraman, R
    Kumar, SP
    Basu, S
    Campbell, DJ
    Berech, J
    INTERNATIONAL TEST CONFERENCE 2002, PROCEEDINGS, 2002, : 1120 - 1129
  • [25] SCAN-BASED TRANSITION TEST
    SAVIR, J
    PATIL, S
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1993, 12 (08) : 1232 - 1241
  • [27] Transition test generation using replicate-and-reduce transform for scan-based designs
    Abadir, M
    Zhu, JH
    21ST IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2003, : 22 - 27
  • [28] Low overhead design-for-testability for scan-based delay fault testing
    Yang Decai
    Chen Guangiu
    Xie Yongle
    JOURNAL OF SYSTEMS ENGINEERING AND ELECTRONICS, 2007, 18 (01) : 40 - 44
  • [29] Improving transition delay fault coverage using hybrid scan-based technique
    Ahmed, N
    Tehranipoor, M
    DFT 2005: 20TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, 2005, : 187 - 195
  • [30] The Technology Research of Remote Automatic Detection and Fault Diagnosis based on JTAG Boundary Scan
    Wang, Daichuan
    Zhang, Pizhuang
    2010 SYMPOSIUM ON SECURITY DETECTION AND INFORMATION PROCESSING, 2010, 7 : 270 - 274