共 50 条
- [21] Static test compaction for scan-based designs to reduce test application time JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2000, 16 (05): : 541 - 552
- [22] Is state mapping essential for equivalence checking custom memories in scan-based designs? 20TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2002, : 275 - 280
- [23] Static Test Compaction for Scan-Based Designs to Reduce Test Application Time Journal of Electronic Testing, 2000, 16 : 541 - 552
- [24] Scan-based transition fault testing - Implementation and low cost test challenges INTERNATIONAL TEST CONFERENCE 2002, PROCEEDINGS, 2002, : 1120 - 1129
- [27] Transition test generation using replicate-and-reduce transform for scan-based designs 21ST IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2003, : 22 - 27
- [29] Improving transition delay fault coverage using hybrid scan-based technique DFT 2005: 20TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, 2005, : 187 - 195
- [30] The Technology Research of Remote Automatic Detection and Fault Diagnosis based on JTAG Boundary Scan 2010 SYMPOSIUM ON SECURITY DETECTION AND INFORMATION PROCESSING, 2010, 7 : 270 - 274