Efficient Hardware Implementation of Morphological Reconstruction based on Sequential Reconstruction Algorithm

This work presents a hardware implementation of the morphological reconstruction algorithm for biomedical images analysis. The morphological reconstruction algorithm is based on the Sequential Reconstruction (SR). In this case, a hardware architecture has been developed and implemented by mapping the SR algorithm into an Altera Cyclone IV E FPGA based platform, including a NIOS II processor. The developed architecture has been described in VHDL language, and it is scalable for image sizes from 96 x 96 pixels to 288 x 288 pixels using a neighboring element of 3 x 3. The quality evaluation of the yielded images was achieved by using SR-SIM (Spectral Residual Based Similarity) metric, which has also been used for visual verification of the images.