STEREO VISION IP DESIGN FOR FPGA IMPLEMENTATION OF OBSTACLE DETECTION SYSTEM

Stereo vision IP (Intellectual Property) modules and obstacle detection systems using stereo vision is an important issue in intelligent vehicle, robots navigation and automotive. In this paper, we proposed an IP module with four (4) known stereo vision algorithms. The four algorithms architectures are compared in term of resources utilization and processing speed (frequency). We developed a software interface for VHDL code generation with needed IP parameters. The proposed IP-Based hardware architecture combines the stereo vision IP to compute the disparity map with V-disparity image and simplified Hough transform for obstacle detection. The proposed system was tested using Virtex-II FPGA based prototyping board. Resources utilization and speed are estimated for different parameters of the disparity map algorithm.