Design of Wideband Continuous-Time ΔΣ ADCs Using Two-Step Quantizers

Continuous-time delta sigma (CT-Delta Sigma) ADCs are established as the data conversion architecture of choice for the next-generation wireless applications. Several efforts have been made to simultaneously improve the bandwidth and dynamic range of Delta Sigma ADCs. We proposed using two-step quantizer in a single-loop CT-Delta Sigma modulator to achieve higher conversion bandwidth. This paper presents a tutorial for employing the design technique through a 130n CMOS implementation. The proposed 640 MS/s, 4th order continuous-time delta sigma modulator (CT-Delta Sigma M) incorporates a two-step 5-bit quantizer, consisting of only 13 comparators. The CT-Delta Sigma M achieves a dynamic range of 70 dB, peak SNDR of 65.3 dB with 32 MHz bandwidth (OSR = 10) while consuming only 30 mW from the 1.2 V supply. The relevant design trade offs have been discussed and presented with simulation results.