Two-step continuous-time incremental sigma-delta ADC

被引：2
|
作者：
Tao, S. [1 ]
Rodriguez, S. [1 ]
Rusu, A. [1 ]
机构：
[1] KTH Royal Inst Technol, Sch ICT, Stockholm 16440, Sweden
来源：
ELECTRONICS LETTERS | 2013年 / 49卷 / 12期
基金：
瑞典研究理事会;
关键词：
D O I：
10.1049/el.2013.1096
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A two-step continuous-time (CT) incremental sigma-delta (I Sigma Delta) ADC, which enhances the performance of conventional CT I Sigma Delta ADCs, is proposed. By pipelining two second-order CT I Sigma Delta ADCs, the proposed two-step architecture can achieve high resolution without sacrificing the conversion rate. Compared to other alternatives, the two-step CT I Sigma Delta ADC exhibits the freedom of adjusting its accuracy and speed independently while featuring quite relaxed circuit specifications.
引用
收藏
页码：749 / 750
页数：2
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