High performance in tree-based parallel architectures

The integrated schema called ''complex node'' couples twin processors, which share a dual-port memory supporting a bidirectional, high-speed communication link. The paper considers the contribution of this device to tree-structured processor hierarchies. As shown by theoretical analysis, increased complex node performance may ensure optimality under reasonable conditions in terns of connectivity and memory speed, which can be easily attained by commercial equipment. This endows the overall research with additional value from a technical point of view. The integrated approach has been implemented by using transputers for experimental development; related advantages in a specific application (implementation of associative models) are also highlighted.