High-Performance and Scalable System Architecture for the Real-Time Estimation of Generalized Laguerre-Volterra MIMO Model From Neural Population Spiking Activity

被引:14
|
作者
Li, Will X. Y. [1 ]
Chan, Rosa H. M. [1 ]
Zhang, Wei [1 ]
Cheung, Ray C. C. [1 ]
Song, Dong [2 ]
Berger, Theodore W. [2 ]
机构
[1] City Univ Hong Kong, Dept Elect Engn, Hong Kong, Hong Kong, Peoples R China
[2] Univ So Calif, Ctr Neural Engn, Dept Biomed Engn, Los Angeles, CA 90089 USA
关键词
Field programmable gate array (FPGA); generalized Laguerre-Volterra model; IP library; multiple-input multiple-output (MIMO) system; neuroscience; IDENTIFICATION; POTENTIATION; RECEPTOR;
D O I
10.1109/JETCAS.2011.2178733
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A hardware-based computational platform is developed to model the generalized Laguerre-Volterra (GLV) multipleinput multiple-output (MIMO) system which is essential in identification of the time-varying neural dynamics underlying spike activities. Time cost for model parameters estimation is greatly reduced by a significant enhancement of 3.1 x 10(3) x in data throughput of the Xilinx XC6VSX475T field programmable gate array (FPGA)based system compared to a C model running on an Intel i7-860 Quad Core processor. The processing core consists of a first stage containing a vector convolution and MAC (multiply and accumulation) component; a second stage containing a prethreshold potential updating unit with an error approximation function component; and a third stage consisting of a gradient calculation unit. The hardware platform is scalable with the utilization of different number of processing units within each stage. It is also easily extendable into a multi-FPGA structure to further enhance the computational capability. A hardware IP library is proposed for versatile neural models and applications. The implementation of the self-reconfiguring platform and its applications to future research of neural dynamics are explored.
引用
收藏
页码:489 / 501
页数:13
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