Digital Predistortion Based on a Compressed-Sensing Approach

A two-block structure is proposed for the digital predistortion (DPD) of power amplifiers (PAs), composed by a weakly nonlinear Volterra-based DPD with memory followed by a memoryless (ML) DPD, combined with the use of compressed-sensing (CS) techniques for the estimation of Volterra kernels. The ML-DPD is obtained from cubic smoothing splines fitted to the static inverse PA characteristic, while the memory-DPD uses a reduced set of coefficients of a fifth-order full Volterra (FV) model with fading memory. CS methods are utilized to find the support set of the active FV model coefficients. This approach has been applied to the DPD of a class J PA operating at 850 MHz with test signals following the LTE-downlink standard. Measurement results show an improvement of over 17 dB in the adjacent channel power ratio, an enhancement of the error vector magnitude from 9.7 % to 1.4 % and retaining only 35 % of the coefficients compared to the complete weakly FV DPD.