A Novel Low Power 3 Transistor based Universal Gate for VLSI Applications

被引：0

作者：

Priya, M. Geetha ^{[1
]}

Baskaran, K. ^{[2
]}

机构：

[1] Amrita Vishwa Vidyapeetham, Coimbatore, Tamil Nadu, India

[2] Govt Coll Technol, Coimbatore, Tamil Nadu, India

来源：

JOURNAL OF SCIENTIFIC & INDUSTRIAL RESEARCH | 2013年 / 72卷 / 04期

关键词：

low power; CMOS; pass-transistor; NAND; delay; flash memory; LOGIC; CIRCUITS; DESIGN;

D O I：

暂无

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

NAND and NOR gates are the two universal logic gates and any other logic gates can be built using them. This paper presents a novel three transistors (3T) based NAND gate with exact output logic levels, yet maintaining comparable performance than the other available NAND gate logic structures. The new logic is characterized by superior speed and low power which can be easily fabricated for Very Large Scale Integration (VLSI) designs. The simulation tests were performed by employing standard 90nm CMOS process technology.

引用

页码：217 / 221

页数：5

共 50 条

[1] A new universal gate for low power SoC applications
M GEETHA PRIYA
K BASKARAN
Sadhana, 2013, 38 : 645 - 651
[2] A new universal gate for low power SoC applications
Priya, M. Geetha
Baskaran, K.
SADHANA-ACADEMY PROCEEDINGS IN ENGINEERING SCIENCES, 2013, 38 (04): : 645 - 651
[3] Design of low power digital VLSI circuits based on a novel Pass-transistor Logic
Song, MK
Asada, K
IEICE TRANSACTIONS ON ELECTRONICS, 1998, E81C (11) : 1740 - 1749
[4] A novel, clustered insulated gate bipolar transistor for high power applications
Narayanan, EMS
Sweet, MR
Luther-King, N
Vershinin, K
Spulber, O
De Souza, MM
Bose, JVSC
2000 INTERNATIONAL SEMICONDUCTOR CONFERENCE, VOLS 1 AND 2, CAS 2000 PROCEEDINGS, 2000, : 173 - 181
[5] Double-Gate Junctionless Transistor for Low Power Digital Applications
Baruah, Ratul Kumar
Paily, Roy P.
2013 1ST INTERNATIONAL CONFERENCE ON EMERGING TRENDS AND APPLICATIONS IN COMPUTER SCIENCE (ICETACS), 2013, : 23 - 26
[6] Low power digitally controlled oscillator designs with a novel 3-transistor XNOR gate
Kumar, Manoj
Arya, Sandeep K.
Pandey, Sujata
JOURNAL OF SEMICONDUCTORS, 2012, 33 (03)
[7] Low power digitally controlled oscillator designs with a novel 3-transistor XNOR gate
Manoj Kumar
Sandeep K.Arya
Sujata Pandey
半导体学报, 2012, 33 (03) : 52 - 59
[8] Novel CMOS composite transistor for low voltage low power applications
Ismail, AM
Soliman, AM
FREQUENZ, 2001, 55 (7-8) : 219 - 223
[9] A Novel Design of Low Power FINFET Adiabatic Circuits for VLSI Applications
Madhuri
Sunila, D.
Venkatesh, G.
Babu, M. Rajan
2017 INTERNATIONAL CONFERENCE OF ELECTRONICS, COMMUNICATION AND AEROSPACE TECHNOLOGY (ICECA), VOL 2, 2017, : 440 - 443
[10] LEakage Control TRAnsistor (LECTRA): A novel Approach for Leakage Reduction in Low Power VLSI Design
Kassa, Sankit R.
Nagaria, R. K.
JOURNAL OF ACTIVE AND PASSIVE ELECTRONIC DEVICES, 2016, 11 (01): : 53 - 77

← 1 2 3 4 5 →