A Compact Model for Superconductor- Insulator-Superconductor (SIS) Josephson Junctions

被引：13

作者：

Alam, Shamiul ^{[1
]}

Jahangir, Mohammad Adnan ^{[1
]}

Aziz, Ahmedullah ^{[1
]}

机构：

[1] Univ Tennessee, Dept Elect Engn & Comp Sci, Knoxville, TN 37996 USA

来源：

IEEE ELECTRON DEVICE LETTERS | 2020年 / 41卷 / 08期

关键词：

Junctions; Josephson junctions; Integrated circuit modeling; Mathematical model; Cryogenics; Superconducting integrated circuits; Compact model; cryogenic memory; Josephson junction; qubit; RCSJ model; Verilog-A; FREQUENCY; MILLIMETER;

D O I：

10.1109/LED.2020.3002448

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present a Verilog-A based compact model for the superconductor-insulator-superconductor (SIS) Josephson junction. The model can generate both hysteretic and non-hysteretic current-voltage (I-V) response for the SIS junctions utilizing the Stewart-McCumber parameter. We calibrate our model with different SIS samples and demonstrate accurate matching between the simulated and experimental results. We implement temperature effect on the energy gap and the critical current of the superconductor to explore the dynamic trends in device characteristics. We calculate the junction inductance and energy as functions of junction current and temperature. We simulate the read/write operations of an SIS junction based cryogenic memory cell to illustrate the usability of our model.

引用

页码：1249 / 1252

页数：4

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