Fused Modulo 2n+1 Add-Multiply Unit For Weighted Operands

被引：0
|
作者：
Pekmestzi, Kiamal [1 ]
Tsoumanis, Kostas [1 ]
Efstathiou, Constantinos [2 ]
机构：
[1] Natl Tech Univ Athens, Sch Elect & Comp Engn, Athens, Greece
[2] Technol Inst Athens, Dept Elect Engn, Athens, Greece
来源：
2016 11TH IEEE INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA (DTIS) | 2016年
关键词：
IMPLEMENTATION;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Digital Signal Processing (DSP) applications are dominated by complex arithmetic operations, which heavily degrade their performance. Targeting to accelerate the execution of Residue Number Systems (RNS)-based DSP applications, in this work, we focus on optimizing the design of the modulo 2(n) + 1 Add-Multiply (AM) operation with weighted operands. We incorporate in our design a new direct recoding of the modulo 2(n) + 1 sum of two weighted operands in its Modified Booth form. Compared to the conventional design of first instantiating an adder and then, driving its output to a multiplier, the proposed fused AM design yields considerable delay, area and power gains.
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页数：6
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