Design of high-yield defect-tolerant self-assembled nanoscale memories

Self-assembled nanoscale memories experience a high degree of hard defects compared to microscale memories. These defects degrade the yield and, along with operational faults, degrade the mean time to failure (MTTF). The common way to tolerate these defects is to reconfigure the defective elements with spares. Hence, the amount of spares is very important and a systematic yield-driven design approach to decide the amount and the allocation of these spares is essential. In this paper, we develop such a design method. We formulate a probabilistic model for the reliability of a memory considering an unclustered defect distribution with Error Correcting Code and reconfiguration using spares local to the lowest hierarchical sub-unit. Using this model, we estimate the yield and MTTF of the memory and develop a method to design the memory for high yield.