SuperV back-end design flow based on Astro

被引：0

作者：

Wang, DH ^{[1
]}

Yu, Q ^{[1
]}

Hong, Y ^{[1
]}

Hou, CH ^{[1
]}

机构：

[1] Chinese Acad Sci, Inst Acoust, Beijing 100080, Peoples R China

来源：

INTERNATIONAL SYMPOSIUM ON COMMUNICATIONS AND INFORMATION TECHNOLOGIES 2005, VOLS 1 AND 2, PROCEEDINGS | 2005年

关键词：

DSP; microprocessor; design flow; timing; crosstalk;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In deep sub-micron VLSI design, designers must face many challenges including timing, area, power, IR drop, crosstalk, etc. A back-end design now is put forward based on Astro. The flow has been used in SuperV DSP microprocessor back-end design for timing optimization, area and IR drop reduction, crosstalk prevention, etc. The final chip includes more than 1 million gates. The area is 5mmx5mm. The clock frequency is up to 266MHz, and power dissipation no more than I watt.

引用

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页码：1477 / 1480

页数：4

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