Why is combinational ATPG efficiently solvable for practical VLSI circuits?

被引:4
|
作者
Prasad, MR [1 ]
Chong, P [1 ]
Keutzer, K [1 ]
机构
[1] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA
基金
加拿大自然科学与工程研究理事会;
关键词
combinational ATPG; SAT; backtracking; complexity analysis; VLSI circuits;
D O I
10.1023/A:1012820722053
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Empirical observation shows that practically encountered instances of combinational ATPG are efficiently solvable. However, it has been known for more than two decades that ATPG is an NP-complete problem (Ibarra and Sahni, IEEE Transactions on Computers, Vol. C-24, No. 3, pp. 242-249, March 1975). This work is one of the first attempts to reconcile these seemingly disparate results. We introduce the concept of cut-width of a circuit and characterize the complexity of ATPG in terms of this property. We introduce the class of log-bounded width circuits and prove that combinational ATPG is efficiently solvable on members of this class. The class of of log-bounded width circuits is shown to strictly subsume the class of k-bounded circuits introduced by Fujiwara (International Symposium on Fault-Tolerant Computing, June 1988, pp. 64-69). We provide empirical evidence which indicates that an interestingly large class of practical circuits is expected to have log-bounded width, which ensures efficient solution of ATPG on them.
引用
收藏
页码:509 / 527
页数:19
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